1. Field of the Invention
The present invention relates to a semiconductor memory device in synchronization with an external clock signal and its control method, and relates in particular to synchronous DRAM (Synchronous Dynamic Random Access Memory: SDRAM) which reads or writes data synchronously with the external clock signal and its control method for writing data.
2. Description of the Related Art
The conventional DRAM inputs or outputs data independently (Asynchronous) from the clock signal supplied to a system, thereby preventing the input of following addresses until the data corresponding to the address is output from an address input. Thus the cycle time of a data transfer depends upon the access time up to the data output, thus causing a difficulty in the improvement of data transfer rate. For this reason, along with a remarkable improvement of processing speed of a processing unit (MPU) installed in the personal computer (PC) in recent years, the improvement of the data transfer speed of the DRAM used as a main memory in the PC arises as an important object.
To address this problem, a SDRAM with the column access path divided into several pipelines and the read/write process between each pipelines synchronized with the rising edge of the external clock signal supplied from the system side has been developed. Furthermore, with no change in the basic architecture of the circuit, a SDRAM in DDR mode (Double Data Rate) which inputs or outputs the data synchronously with both the rising and falling edges of the external clock signal (CLK) is developed (for example, described in particular in Japanese Application No. 9-167451, Japanese Application No. 10-22257, etc.) The data transfer rate of the SDRAM in the DDR mode has an advantage of being approximately twice as fast as that of the SDRAM in which the data is synchronized in transmission only with the rising edge of the external clock signal (hereinafter called SDR mode for convenience), thus becoming the present mainstream of the SDRAM.
Now, these semiconductor memory devices are tested and evaluated by memory test equipment (IC tester) in the manufacturing stage. The memory test equipment""s functions include counting the number of defective memory cells and judging whether the repair of the defective memory cells is feasible under a situation identical to the normal operative condition. For example, in testing for the defective memory cells in the SDRAM, the memory test equipment generates a signal identical to the external clock signal CLK used during the actual operation of the SDRAM and input it to the SDRAM. It should be noted that a wafer test checks all chips formed on a semiconductor wafer and tests writing and reading of the predetermined data to each chip.
However, the above-mentioned SDRAM having the DDR mode is quite different from the SDRAM having the conventional SDR mode in operations. Especially in the write/read operation, since the DDR mode generates the write/read data in frequency twice that of the conventional type, it is required to newly introduce the memory test equipment which can generate the clock signal for a test corresponding to the DDR mode. This in turn requires the purchase of new memory test equipment for manufacturing SDRAM in the DDR mode, so resulting in higher investment in equipment and increasing the cost of the SDRAM having the DDR mode. Also, the inability of using the conventional memory test equipment causes a delay in product development of the DDR mode SDRAM.
More specifically, there is a restriction that only one strobe can be generated within one clock in the semiconductor tester. When the SDRAM is tested with DDR method under such restriction, two outputs are provided in one clock, requiring the use of two clocks from the semiconductor tester as one clock and to generate two strobes within one clock of clocks given to the semiconductor memory device. That is, the test must be executed by operating the semiconductor memory device in half the frequency of the actual tester ability.
FIG. 21 is a timing chart showing a comparison between the data reading tests in the wafer test of the semiconductor memory device regarding to an embodiment of the prior and present inventions. FIG. 22 is a timing chart showing a comparison between the data writing tests in the wafer test of the semiconductor memory device regarding to an embodiment of the prior and present inventions. Here, FIG. 21(a) and FIG. 22(a) are the timing charts of the data reading and data writing tests of the SDRAM in the DDR type which is a conventional semiconductor memory device, and FIG. 21(b) and FIG. 22(b) are the timing charts of the data reading and data writing tests of the SDRAM of the DDR type which is a semiconductor memory device as an embodiment of the present invention later described.
As shown in FIG. 21(a), since the conventional data reading test in the wafer test of the SDRAM having the DDR type can execute only the reading operation in the DDR type, it, for example, gives a clock (a device clock) CLK which has a cycle (T=2xt) twice as long as the main clock (a tester clock) clk of the semiconductor tester to the SDRAM in the DDR type to read twice standing two strobes (STB) to one clock of this device clock CLK. Here, when a CAS latency is 1.5 clocks (CL=1.5) and a bus length is 8 (BL=8: when 8 different data are read), the completion of a series of data readings requires a time equivalent to 13 clk""s after an active state.
Also, as shown in FIG. 22(a), the conventional data writing test in the wafer test of the SDRAM having the DDR type allows only the write operation in the DDR type, therefore, for example, two write operations are executed during one clock of this device clock CLK by giving a device clock CLK which has a cycle (T=2xt) twice as long as that of the tester clock clk. Here, When the 8 different data are written by delayed write, the completion of a series of write operations requires a time equivalent to 13 clk""s (tester clocks) after active state.
By the way, since the wafer test is required for all chips formed on the semiconductor wafer, testing by operating the device with a half the frequency of the actual semiconductor tester like this leads to a problem to introduce an increase in manufacturing cost. For example, testing the SDRAM of the DDR type under the ordinary operation requires expensive test equipment that has a frequency band twice as fast as the operation speed of the SDRAM, which consequently increases the manufacturing cost of the SDRAM of the DDR type significantly. Use of the ordinary test equipment, on the other hand, requires all device clocks CLK to be operated with a half the frequency of the tester clock clk and a redundant timing must be set in all tests. Consequently, the test time becomes longer and also the manufacturing cost of the devices is increased.
An object of the present invention is to provide a semiconductor memory device that can be easily tested and evaluated by the conventional memory test equipment and its control method, while having a transfer mode to transfer data in synchronization with the rising and falling edges of the external clock.
A further object of the present invention is to provide a semiconductor memory device that can reduce the test time without the use of expensive test equipment.
The above objects are achieved by a semiconductor memory device operable in synchronization with an external clock signal, comprising a data transfer circuit, having a first transfer mode and a second transfer mode, for transferring data in synchronization with rising and falling edges of an external clock signal in the first transfer mode, and for transferring data in synchronization with only one of the rising and falling edges in the second transfer mode. Also, in the semiconductor memory device of the present invention, the data transfer circuit switches the first and second transfer modes in response to a mode switch signal. According to this structure, the conventional memory test equipment can be used to test and evaluate the semiconductor memory device by switching to the second transfer mode. In an actual use, it is also possible to realize a high-speed data transfer rate by switching to the first transfer mode.
Further, in the semiconductor memory device of the present invention, the mode switch signal is generated on the basis of a setting signal input from outside the device. Furthermore, the semiconductor memory device of the present invention has a register to latch the setting signal. By forming such a structure, the transfer mode of the data transfer circuit can easily be switched from the system side which utilizes the semiconductor memory device.
In the semiconductor memory device of the present invention, an empty register in a mode register can be used as the register. It is possible to easily maintain the mode switch signal by utilizing the empty register of the mode register arranged also in the conventional SDRAM. Or, by arranging a switch signal input terminal to the semiconductor memory device of the present invention and by inputting a mode switch signal from the system side to the switch signal input terminal, the transfer mode of a direct data transfer circuit may be switched from the system side. By doing like this, the circuit structure of the semiconductor memory device can be more simply formed.
In the semiconductor memory device of the present invention, the second transfer mode may transfer data in synchronization with the rising and falling edges of the external clock signal. By doing this, the transfer rate of half that of the first transfer mode can be realized with a duty ratio of the external clock equal to 50%.
Also, in the semiconductor memory device of the present invention, the data transfer circuit has a data input converter, for simultaneously transferring parallel data converted from serial data which are input serially in the first transfer mode, and for sequentially transferring the serial data in the second transfer mode. By forming this structure, even in the first transfer mode which inputs or outputs data at the transfer rate twice as fast as that of the second transfer mode to the external (system side), the same write or read speed as that of the second transfer mode can be used for the memory cells in the semiconductor memory device.
Furthermore, in the semiconductor memory device of the present invention, the data transfer circuit has a data input clock generating circuit, for generating a first clock signal in the first transfer mode or a second clock signal in the second transfer mode in response to the mode switch signal, and for transmitting the first clock signal or the second clock signal to the data input converter. By using the clock signal, a data input operation at the data input converter in the first or second transfer mode can be easily changed by a simple circuit structure.
Also, in the semiconductor memory device of the present invention, the data transfer circuit has a write control circuit, for generating a first write enable signal to simultaneously transfer the parallel data to a memory cell array in the first transfer mode, and for generating a second write enable signal to sequentially transfer the serial data to the memory cell array in the second transfer mode. Thus, since a write enable signal in response to the first and second transfer modes are output on the basis of the mode switch signal, data can surely be transferred in both of the first and second transfer modes in synchronization with a data input converter which executes a data input operation by the clock signal on the basis of the mode switch signal also.
Further in the semiconductor memory device of the present invention, the semiconductor memory device comprises a column address counter which can change a timing to count up a column address in response to the mode switch signal.
Furthermore, a column address counter of the present invention comprises a clock generating circuit supplying a first internal address generating clock and a second internal address generating clock, a first address generating section generating a first internal address in synchronization with the first internal address generating clock, and a second address generating section generating a second internal address in synchronization with the second internal address generating clock. Furthermore, the clock generating circuit comprises a clock generator and a frequency divider, the clock generator generating an internal clock in response to the external clock, the frequency divider receiving the internal clock and generating a divided clock, and wherein the clock generating circuit outputs the internal clock as the first internal address generating clock in the first transfer mode, and outputs the divided clock as the first internal address generating clock and the internal clock as the second internal address generating clock in the second transfer mode.
The semiconductor memory device of the present invention also comprises a burst counter which starts counting the internal clock according to a write or read command, and deactivates the clock generator signal when the predetermined number of the internal clocks is counted. Furthermore, the burst counter comprises a burst length conversion circuit for converting the predetermined number of the internal clocks in response to the mode switch signal.
With this structure, in a burst mode with the predetermined burst length, a counting up of the column address is executed matching with the data transfer rate of the first or second transfer mode, so that a sure data transfer can be possible in each transfer mode.
In the semiconductor memory device of the present invention, the data transfer circuit transfers data to a memory cell array when the data is the write data. When the semiconductor memory device is tested and evaluated, the reason of the data write failure is easily analyzed using the conventional test equipment particularly by switching the first transfer mode to the second transfer mode when data are written.
Also, the above objects are achieved by a control method of the semiconductor memory device operable in synchronization with an external clock signal, comprising transferring data in synchronization with both of rising and falling edges of the external clock signal in a first transfer mode, and transferring the data in synchronization with one of the rising and falling edges in a second transfer mode. According to this control method, since it is possible to switch to the second transfer switch in the test of the semiconductor memory device, the failure analysis of the memory cells is easily made by using the conventional memory test equipment. On the other hand, the first transfer method which can realize a high-speed data transfer rate can be employed in the actual use of the semiconductor memory device.
In this control method, the first and second transfer modes are switched in response to a switch signal which is generated on the basis of a setting signal input from outside of the device or directly input from the outside. Also, the data is transferred in synchronization with the rising edge of the external clock signal in the second transfer mode. Further, in this control method, in the first transfer mode, a plurality of data serially input are converted from serial data to parallel data and the converted parallel data are simultaneously transferred. In the second transfer mode, a plurality of data are sequentially transferred.
Also, in the control method of the semiconductor memory device of the present invention, whether a plurality of data are simultaneously transferred after the serial to parallel conversion or are sequentially transferred is switched in response to the switch signal. Further, in this control method, the step of transferring includes outputting a first write enable signal to a write amplifier in the first transfer mode and outputting a second write enable signal in the second transfer mode in response to a switch signal when the data is transferred to a memory cell array. Furthermore, in the control method of the semiconductor memory device of the present invention, a timing to count up a column address is changed in response to the switch signal.
Also, in this control method, the second transfer mode is selected when the data is written in a test mode.
By employing such control method in the test and evaluation of the semiconductor memory device the cause of the data write failure is easily analyzed using the conventional memory test equipment by switching the first transfer mode to the second transfer mode at the data write.
Above objects are achieved by a semiconductor memory device of a double data rate type for reading the data in response to rising and falling edges of a clock having an operating mode to immediately read the data with a read command.
Also, the above objects are achieved by a semiconductor memory device of a double data rate type for reading data in response to both of rising and falling edges of a clock having a single data rate mode for reading the data in response to one of the rising and the falling edges of the clock.
Also, the above object is achieved by a semiconductor memory device of a double data rate type for writing data in response to both of rising and falling edges of a clock having an operating mode for immediately writing the data after a write command is received.
Further, the above objects are achieved by a semiconductor memory device of a double data rate type for writing data in response to both of rising and falling edges of a clock having a single data rate mode to write data in response to one of the rising and falling edges of the clock.
According to the semiconductor memory device of the present invention, it has not only the double data rate mode but also a mode to read data immediately with a write command.
Also, according to the semiconductor memory device of the present invention, it has not only the double data rate mode but also the single data rate mode to read data in response to one of the rising and falling edges of a clock.
Further, according to the semiconductor memory device of the present invention, it has not only the double data rate mode but also a mode to write data immediately with a write command.
Furthermore, according to the semiconductor memory device of the present invention, it has not only the double data rate mode but also the single data rate mode to write data in response to one of rising or falling edges of a clock.
Thus, according to the present invention, a semiconductor memory device capable of reducing a test time can be provided without the use of expensive test equipment.